Electronic calculator systems of the type wherein all the main electronic functions are integrated on a single integrated semiconductor chip wherein a small number of such chips are described in the following U.S. patents, which are assigned to the assignee of this invention:
U.S. Pat. No. 3,919,532 issued to Michael J. Cochran and Charles P. Grant on Nov. 11, 1975 and entitled "Calculator System Having An Exchange Data Memory Register,"
U.S. Pat. No. 3,934,233 issued to Roger J. Fisher and Jerald D. Rogers on Jan. 20, 1976 and entitled "Read-Only-Memory for Electronic Calculator,"
U.S Pat. No. 3,931,507 issued to George L Brantingham on Jan. 6, 1976 and entitled "Power-Up Clear in Electronic Digital Calculator,"
U.S. Pat. No. 3,988,604 issued to Joseph H. Raymond, Jr. on Oct. 26, 1976 and entitled "Electronic Calculator or Digital Processor Chip Having Multiple Function Arithmetic Unit Output."
The concepts of these prior applications have made possible vast reductions in the cost of the small personal-sized calculators. Continuing efforts to reduce the cost of these products include the development of a calculator chip utilizing minimum semiconductor chip area and which is capable of performing addition, subtraction, multiplication, division, squaring, square rooting, percent and memory operations. The chip disclosed herein may be utilized in hand-held or desk model calculators capable of performing operations of the aforementioned types and may be implemented on a very small semiconductor chip.
The present invention relates to a key debounce system for a microprocessor and, more specifically, a key debounce system for an electronic calculator implemented on a semiconductor chip. An entire electronic calculator system which uses the key debounce system of this invention is disclosed. The electronic calculator system is a serially, word organized calculator; however, the invention is not limited to this type calculator, but rather may be utilized with microprocessors generally which interface with a keyboard or other such input means. A key debounce system is used to inhibit an unintented double entry which might otherwise occur if the key switches at the keyboard bounce when actuated.
In the prior art, as exemplified by U.S. Pat. Nos. 3,919,532; 3,931,507 or 3,988,604 key debounce was controlled by instructions stored in the system's instruction memory. These instructions typically test the state of a latch or flag which is set in response to operation of the calculator's keyboard. The state of the flag or latch is periodically tested to help assure that the calculator or microprocessor ignores key bounces but inputs intended second operations of the same key.
It has been found that the efficacy of these prior art key debounce systems is dependent upon the frequency of the system's clock. That is, within a relatively narrow clock frequency range, such prior art key debounce systems could be made to operate effectively; however, their efficacy was reduced as the variability of the system's clock frequency increased. While this may be of little consequence for a system which uses external means, such as an external resistor or crystal, to control the system's clock frequency, it is of great importance where the system's clock frequency is totally controlled by means of the system's chip or chips. Because of the different variables which enter into the fabrication of a chip, a chip's clock frequency can vary substantially and because it would be undesirable to discard chips otherwise operable whose clock frequency is outside some predetermined narrow range, it is desirable to have a key debounce system having high efficacy over a relatively wide range of system clock frequencies. The use of chips having no external frequency control means is desirable because of the resulting reduction of number of components needed to construct the calculator or microprocessor system.
It was therefore one object of this invention to improve key debounce systems for use with an electronic calculator or microprocessor.
It is another object of this invention to provide a reliable key debounce system for use with an electronic calculator or microprocessor whose clock frequency may vary over a relatively wide range.
It is still another object of this invention to improve key debounce systems used with electronic calculators or microprocessors such that the system's clock generator need no external means to control clock frequency.
The foregoing objects are achieved according to the present invention as is now described. In a preferred embodiment of the invention, an electronic microprocessor or calculator system having a data memory for storing numeric data, an arithmetic unit for performing arithmetic operations on the data stored in the data memory, a program counter, an instruction memory for storing a plurality of instruction words controlling the operation of the microprocessor calculator, one of the plurality of instruction words being outputted once each instruction cycle of the system according to an address stored in the program counter and a keyboard sensing circuit for interfacing the system with a keyboard, is provided with a key debounce system. The key debounce system includes a circuit for loading a starting instruction word address into the program counter, the starting instruction word being generated according to the sensing of the depression of a key at the keyboard by the sensing circuit, the starting instruction word address being the first address of a set of instructions controlling the system performing the function indicated by the key depressed. The key debounce system also includes a disabling circuit for disabling the circuit loading the start instruction word address after the sensing circuit has detected a key depression until an instruction word toward the end of the set of instruction words is outputted and no additional key depression is detected by the sensing circuit for a preselected period having a duration of a plurality of the aforementioned instruction cycles. The enabling circuit, by being continually sensitive to the lack of an additional key depression during a continuous period having the aforementioned plurality of instruction cycles desensitizes the key debounce system to variations in the system's clock frequency. For instance, in the embodiment subsequently disclosed, the frequency of the oscillator in the clock generator may vary from 150KHz to 800KHz with little effect on the efficacy of the disclosed embodiment of the key debounce system.